The present invention relates to a semiconductor memory which has a flip-flop type memory cell and specifically to control of a supply potential which is to be supplied to a memory cell.
In recent years, progress of semiconductor processes has been enhancing finer circuitry and, hence, rapid advance in achieving reduced circuit area of semiconductor integrated circuits and lower supply voltages. For example, in a semiconductor memory which has flip-flop type memory cells, such as static random access memory (SRAM), it has become very difficult for the memory cells to have stable characteristics due to variations in characteristics of transistors constituting the memory cells or decrease of supply voltage. Accordingly, the yield of semiconductor memories disadvantageously decreases due to reduction in static noise margin (SNM) or write margin.
As for the semiconductor memory having such flip-flop type memory cells, a technique of controlling the potential of a high-data retaining supply of the memory cells to achieve easier writing has been proposed. For example, the following conventional techniques have been known. Japanese Laid-Open Patent Publication No. 55-64686 proposes a semiconductor memory wherein the potential of the high-data retaining supply is controlled to be low during a write operation to render the write operation easier. Japanese Laid-Open Patent Publication No. 2007-109300 proposes a semiconductor memory having memory cells each of which includes two inverters wherein the potentials of two high-data retaining supplies each of which is determined according to the level of a bit line connected to the output of a corresponding one of the inverters are applied to the inverters, whereby easier writing is achieved.
FIG. 6 is a circuit diagram showing an example of a structure of a conventional semiconductor memory. The semiconductor memory 900 of FIG. 6 includes a plurality of memory cells 80, word lines WL1 and WL2, first and second bit lines BL and BLX, first and second high-data retaining supply lines VDDM and VDDMX, PMOS (p-channel metal oxide semiconductor) transistors 931 and 932, NMOS (n-channel metal oxide semiconductor) transistors 933, 934, 971 and 972, a selection circuit 950, and inverters 973 and 974. The selection circuit 950 includes AND circuits 951, 952 and 953.
Each of the memory cells 80 includes inverters 86 and 87 and access transistors 93 and 94. The inverter 86 includes a load transistor 81 and a drive transistor 91. The inverter 87 includes a load transistor 82 and a drive transistor 92. The inputs and outputs of the inverters 86 and 87 are cross-coupled with each other to constitute a flip-flop.
FIG. 7 is a timing diagram illustrating a write operation of the semiconductor memory of FIG. 6. In general, writing of data in an SRAM memory cell as shown in FIG. 6 is achieved by decreasing the potential of one of the bit lines BL and BLX, which has been precharged to a high potential (“H”), from “H” to a low potential (“L”) while maintaining the word line WL at “H”.
Before the start of a write cycle, the bit lines BL and BLX are precharged to supply potential VDD by a precharge circuit (not shown). Outputs NBL and NBLX of the inverters 973 and 974 are “L”. The PMOS transistors 931 and 932 are conducting. The potentials of the high-data retaining supply lines VDDM and VDDMX are supply potential VDD.
After the start of the write cycle, the word line WL1 or WL2 is first selected. If the word line WL1 is selected, the potential of the word line WL1 transitions from “L” to “H” so that the access transistors 93 and 94 of the memory cell 80 connected to the word line WL1 become conducting. Meanwhile, address signal AD transitions to “H”, and any of input data signals DIN and DINX transitions to “H”. It should be noted that FIG. 7 shows an example where input data signal DIN transitions to “H”.
Then, write control signal WE transitions to “H” so that the outputs of the AND circuits 951 and 953 of the selection circuit 950 become “H”. As a result, the NMOS transistor 971 becomes conducting so that the bit line BL is discharged from supply potential VDD to the ground potential. Meanwhile, the potential of the bit line BLX stays at the precharged potential, i.e., supply potential VDD. When the potential of the bit line BL reaches the threshold of the inverter 973, output NBL of the inverter 973 transitions to “H” so that the PMOS transistor 931 becomes non-conducting while the NMOS transistor 933 becomes conducting.
As a result, the potential of the high-data retaining supply line VDDM transitions from supply potential VDD supplied by the PMOS transistor 931 to potential VDD-Vtn supplied by the NMOS transistor 933 (where Vtn represents the threshold of the NMOS transistor 933). The potential of the high-data retaining supply line VDDMX on the opposite side stays at supply potential VDD.
Since the potential of the high-data retaining supply line VDDM transitions to a lower level than the potential of the high-data retaining supply line VDDMX, the ability of the inverter 86 of outputting a current decreases. Therefore, even when the potential retained at the output node of the inverter 86 is “H”, writing of “L” in this node through the bit line BL becomes easier. The ability of the inverter 87 of outputting a current is maintained, and thus, inversion of memory data is assisted in the operation of writing “L” through the bit line BL.
However, the semiconductor memory of FIG. 6 disadvantageously requires a long time for writing of data in a memory cell as described below.
In the semiconductor memory of FIG. 6, as illustrated in FIG. 7, after write control signal WE transitions to “H”, the bit line BL transitions to “L” so that output NBL of the inverter 973 transitions to “H”. Accordingly, the NMOS transistor 933 decreases the level of the high-data retaining supply line VDDM. After the bit line BL having a large wire capacitance is driven, the high-data retaining supply line VDDM is driven according to the potential of the bit line BL. Therefore, period T1 which extends between settling of write control signal WE and settling of the potential of the high-data retaining supply line VDDM at a lower level than supply potential VDD is long. Even after the potential of the bit line BL is settled, write control signal WE and the word line WL1 need to be maintained at “H” till the potential of the high-data retaining supply line VDDM is settled and writing of data in the memory cell completes. Thus, as a result, the time required for writing is long.
In the semiconductor memory of FIG. 6, after writing of data in the memory cell is completed, it disadvantageously takes a long time for the decreased potential of the high-data retaining supply line to return to supply potential VDD as described below.
In the semiconductor memory of FIG. 6, as illustrated in FIG. 7, write control signal WE transitions to “L” after writing is completed so that the NMOS transistor 971 becomes non-conducting, and the precharge circuit causes the bit line BL to transition to supply potential VDD. Accordingly, output NBL of the inverter 973 transitions to “L” so that the NMOS transistor 933 becomes non-conducting while the PMOS transistor 931 becomes conducting. As a result, the high-data retaining supply line VDDM returns to supply potential VDD. Since the high-data retaining supply line VDDM is driven according to the potential of the bit line BL, period T2 which extends between transition of write control signal WE to “L” and return of the high-data retaining supply line VDDM to supply potential VDD is long. Thus, the cycle time for writing is also long.